The present invention relates to a nonvolatile multilevel memory and a reading method therefor, in particular for flash memories.
As known, the need for nonvolatile memories with an always increasing density, is leading to design of multilevel memories, wherein data, stored in the floating gate regions of the cells, is coded on several logic levels, by dividing the quantity of charge stored in each cell.
FIG. 1 shows the characteristic linking the gate-source voltage Vgs with the drain-source current Ids of a flash cell, biased in known manner with reading voltages, for a two-level memory, i.e., a memory wherein data is coded in each memory cell by a bit having two possible values, associated respectively with an off and an on condition of the cell, in turn dependent on whether the cell has been programmed. In particular, in FIG. 1, Vtv and Vtw represent the value of the gate-source voltage Vgs at which a flash cell begins to conduct current, respectively for a virgin (erased) cell, and a written cell. In a memory of this type, the logic value xe2x80x9c1xe2x80x9d is generally associated to the characteristic having the threshold voltage Vtv, generally comprised between 0.5 and 2.5 V, and the logic value xe2x80x9c0xe2x80x9d is generally associated to the characteristic having the threshold voltage Vtw, and is generally greater than 5 V.
It is also known that reading a memory cell is based on converting the current flowing in the memory cell, at a specific gate-source voltage Vgs, into a voltage then translated to a CMOS level, at the output of a comparator circuit. An example of a known reading circuit is shown in FIG. 2; the reading circuit 1 comprises a current/voltage converter (comprising a current mirror circuit 2), and a comparator 3; the current mirror circuit 2 has two nodes, connected respectively to a memory cell 4 and to a reference cell 5, as well as to the inputs of the comparator 3, the output whereof supplies the signal at CMOS level, thus coding the read bit.
For multilevel cells, the plane (Vgs, Ids) is divided by several characteristics, as shown for example in FIG. 3, concerning the storage of two bits per cell, corresponding to four logic values 11, 10, 01 and 00. In this case, the four logic values correspond to four different threshold values Vt1, Vt2, Vt3 and Vt4, which in turn are associated with different quantities of charges stored in the floating gate region of the memory cells.
Programming of the cells is affected by uncertainty, and the characteristics both of FIG. 1 and FIG. 3 represent the central value of the actually obtainable distributions; in fact, to each threshold value a respective distribution of values is associated, comprised between a minimum value and a maximum value, and spaced from the maximum values of the preceding distribution, and/or from the minimum value of the successive distribution, to allow correct reading of the cells. In addition, each distribution can have a different amplitude, as shown for example in FIG. 4, showing the distributions associated with memory cells storing each two bits, using a not uniform scale.
Also here, reading comprises converting the current flowing in the cell, into a voltage; the voltage thus obtained is then compared with different intermediate voltage values within the above-described threshold distributions.
One of the problems arising when reading multilevel cells, is caused by the reading voltage applied to the gate terminals of the cells to be read; in fact, at the reading voltage, all the read cells (optionally except the cells programmed to the highest threshold value) must be on, to compare the converted voltage with the various voltage levels; consequently, the reading voltage must be at least greater than the last but one threshold value (Vt3 in FIG. 2; VR in FIG. 4, here of 6V).
FIG. 5 shows the characteristics variability intervals taking into account the distributions of the threshold voltages shown in FIG. 4, as well as three reference current values, IR1, IR2, IR3, (indirectly) compared with the current flowing in the memory cells, at the reading voltage VR. In practice, the three reference current values are intermediate between the different distributions of characteristics.
FIG. 6 shows an example of a reading logic circuit 10, supplying at the output two bits 01, 02 stored in a cell, after comparison with three reference voltages V1, V2, V3, corresponding to the reference current values IR1, lR2, IR3 of FIG. 5.
In detail, the reading logic circuit 10 comprises three comparators 11, 12, 13, receiving at their non-inverting inputs a voltage Vm, obtained from the conversion of the current flowing in a read memory cell and receiving at their inverting input a respective reference voltage V1, V2, V3. The output of the comparator 11 is connected to a first input of a first, three-input AND gate 14; the output of the comparator 12 defines a first output 15 of the reading logic circuit 10, and is connected to a second input of the first AND gate 14, via a first inverter 16; the output of the comparator 13 is connected to a third input of the first AND gate 14, and to an input of a second, two-input AND gate 17. The output of the first AND gate 14 is connected to a second input of the second AND gate 17, via a second inverter 18. Thereby, the output 15 of the reading logic circuit 10 supplies the first bit 01; the output of the second AND gate 17 defines a second output 19 of the reading logic circuit 10, and supplies the second bit 02.
The memory cells of the considered type have small gain (20xcexcA/V); in addition, the present architectures require that the reading voltage VR (at least equal to the lower limit of the threshold voltage distribution that is furthest to the right in FIG. 5, as previously explained), should not be too high. These conditions are a problem when reading cells storing four levels (two bits); in fact, it is necessary to distinguish currents differing from one another by 10 xcexcA, but have different common mode contributions, since the difference between the different currents is always 10 xcexcA, but the absolute value varies between 0 and 70 xcexcA. The distinction is also made more complex by the gain variations associated with the various threshold voltages.
In known circuits, used for reading cells storing one or two bits, the current/voltage converter connected to the cell, and the comparators connected with the converter, are optimized on the basis of the present current and voltages. However, this solution is difficult to implement for cells storing more than four levels, in particular when a cell access time (overall reading time) is to be ensured of approximately 100-200 ns, as in the present circuits.
FIG. 7 refers to the storage of three bits per cell, corresponding to eight different threshold voltages (eight different binary words), and shows the threshold voltage variability intervals for the various binary words, ignoring the spacing necessary to avoid reading uncertainties. FIG. 7 also shows a possible distribution of the characteristics for the binary word 101.
Instead of using a constant value reading voltage, reading may be effected here by increasing the voltage applied to the gate terminal of the cell to be read from the upper distribution limit of the lower threshold voltage (for example 2 V in FIG. 7), to the lower distribution limit of the higher threshold voltage (6 V in FIG. 7). The reading voltage VR can be increased according to a continuous or discrete ramp; in the latter case (FIG. 8), the number of steps of the voltage ramp can be equivalent to the number of programmable threshold voltage levels, less one (seven, in this case).
In particular, the memory cell can be read using a reading circuit 23 shown in FIG. 9; in detail, the reading circuit 23 comprises a voltage/current converter 24, comprising two diode-connected PMOS transistors 25, 26, arranged between supply line 28, set to VCC, and, respectively, a constant current source 29 (supplying current I, for example 10 xcexcA), and the drain terminal of a cell 30 to be read. The cell 30 to be read has a source terminal connected to ground, and a gate terminal connected to the output of a ramp voltage generator, here formed by a digital/analog converter (DAC) 31; the input of DAC 31 receives a binary signal, specifying the value of the voltage VR to be generated as output, and is also connected to an input of a latch circuit 32. Latch circuit 32 has an enable input EN connected to the output of a comparator 33; the comparator 33 has a non-inverting input connected to the gate terminal of the transistor 25, and an inverting input connected to the gate terminal of the transistor 26.
Thereby, when the current flowing in the cell 30 exceeds the current I generated by the constant current source 29, the comparator 33 switches, by blocking, in the latch 32, the binary value of the ramp voltage VR applied then to the cell 30 to be read, and subsequently supplied as output.
By defining as the threshold of the cell 30 to be read the gate-source voltage Vgs at which the cell 30 absorbs a current value I, the comparator 33 checks whether the threshold of the cell 30 is in the area of the plane in FIG. 8 corresponding to row voltage VR applied at that moment. This operation requires one reading circuit 23 (sense amplifier) per cell, i.e., every three bits, instead of one reading circuit for every bit, as in the two-level memories of known type, thus saving a considerable amount of area.
If the cell stores binary word 101, as in the example considered in FIG. 7, the comparator 33 switches to the third level of row voltage VR (of 3.3 V in the example).
The row voltage steps, which are seven in number, can have a duration of 15 ns, ns, taking the output time of row voltage VR to 105 ns, compared with the 30 ns at present. This delay is compensated by the fact that three bits, instead of one, are simultaneously read.
The solution shown in FIG. 9 functions for up to three bits per cell, i.e., eight levels, but it cannot be applied to a greater number of levels, since the access time would become too long. In addition, the duration for each voltage step cannot be reduced below a given value, to ensure efficient reading of the cells.
FIG. 10 shows a known architecture of a nonvolatile memory 40, comprising a global row decoder 41; a column decoder 42, and a memory array 43, comprising a plurality of sectors (of which only two, indicated as 44a and 44b, are shown in the figure). The global row decoder 41 is connected to a plurality of global word lines 46, and the column decoder 42 is connected to a plurality of bit lines 47. Each global word line 46 is associated, for each sector 44a, 44b, to a pair of local word lines 48a, 48b, selected individually and alternately, according to address signals supplied from the exterior, via a local row decoder 45a, 45b associated with the respective sector 44a, 44b. 
With an architecture of this type, each binary word (byte) is stored in cells arranged on a same row within a single sector, but on different columns, as shown schematically in FIG. 10 by bit lines 47 relative to bits 0 and 7 of the words stored in sectors 44a and 44b. Thereby, a byte is read by switching on the cells arranged on a row and by converting individually into voltage the current flowing through these cells, present on the respective bit lines 47.
An object of the invention is thus to provide a memory and a reading method which eliminate the disadvantages of the known methods and devices, thus allowing reading of multi-level cells quickly and reliably.
The multilevel memory stores words formed by a plurality of binary subwords in a plurality of cells, each cell having has a respective threshold value. The cells are arranged on cell rows and columns, are grouped into sectors divided into sector blocks, and are selected via a global row decoder, a global column decoder, and a plurality of local row decoders, which simultaneously supply a ramp voltage to a biasing terminal of the selected cells. Threshold reading comparators are connected to the selected cells, and generate threshold attainment signals when the ramp voltage reaches the threshold value of the selected cells; switches, are arranged between the global word lines and local word lines, opening of the switches is individually controlled by the threshold attainment signals, thereby the local word lines are maintained at a the threshold voltage of the respective selected cell, after opening of the switches.